1、状态转换图

2、verilog程序

 　　1）源程序

1 module seqdet(x,z,clk,rst); 2 input x,clk,rst; 3 output z; 4  5 reg[2:0] state; 6 wire z; 7  8 parameter   idle=3'd0, 9             a=3'd1,10             b=3'd2,11             c=3'd3,12             d=3'd4,13             e=3'd5,14             f=3'd6;15 16 assign z=((state==d)&&(x==0))? 1:0;   17  18 always@(posedge clk or negedge rst)19     begin20         if(!rst) 21             begin22                 state<=idle;23             end24         else25             casex(state)26                 idle:27                     if(x==1) state<=a;28                     else state<=idle;29                 a:30                     if(x==0) state<=b;31                     else state<=a;32                 b:33                     if(x==0) state<=c;34                     else state<=a;35                 c:36                     if(x==1) state<=d;37                     else state<=idle;38                 d:39                     if(x==0) state<=e;40                     else state<=a;41                 e:42                     if(x==0) state<=f;43                     else state<=a;44                 f:45                     if(x==0) state<=idle;46                     else state<=d;47                     48             endcase 49     end50 51 endmodule

 

　

　2）.v的测试程序

　　

1 `timescale 1ns/1ns 2 `define halfperiod 20 3  4 module t; 5  6 reg clk,rst; 7 reg[23:0] data; 8 wire z,x; 9 10 assign x=data[23];11 12 initial13     begin14         clk=0;15         rst=1;16         #2 rst=0;17         #30 rst=1;18         data=20'b1100_1001_0000_1001_0100;19         #(`halfperiod*1000)20         $stop;21         22     end23     24 always #(`halfperiod) clk=~clk;25 26 always@(posedge clk)27     #2 data={data[22:0],data[23]};//移位的一种方法28 29 seqdet m(.x(x),.z(z),.clk(clk),.rst(rst));30 31 32 33 34 35 endmodule

 

 

3、总结

　　画出状态图就好了，.v的文件直接添加到testbench里就可以仿真。